EDN

Challenges for ESD-Robust Design in State-of-the-Art Analog Technologies

As the popularity of portable electronics, “smart devices”, and automotive electronics keeps increasing, so does the need for analog functions to be embedded in ICs. This drives the demand for ...
Design-Reuse

Sarnoff's 65nm CMOS TakeCharge ESD Solution licensed to Fujitsu, Japan

GISTEL, Belgium -- November 17, 2006 -- Sarnoff Europe (www.sarnoffeurope.com) today announced that it has licensed its on-chip electrostatic discharge (ESD) protection portfolio, TakeCharge® to ...
Business Wire

Research and Markets: Electrostatic Discharge (ESD): A Comprehensive Design and Synthesis Guide for Semiconductor, Circuit & ESD Engineers

DUBLIN--(BUSINESS WIRE)--Research and Markets (http://www.researchandmarkets.com/research/22f186/esd_design_and_sy) has announced the addition of John Wiley and Sons ...
Design-Reuse

Sarnoff Europe and UMC Sign IP Alliance for ESD Protection

GISTEL, Belgium & HSIN CHU, Taiwan -- June 05, 2007-- Sarnoff Europe (www.sarnoffeurope.com) today announced that it has signed an agreement with UMC to make available its on-chip ESD protection ...
Business Wire

New Advanced SPICE Model for ESD Diodes Addresses Challenges in IC Design and Protection

AUSTIN, Texas--(BUSINESS WIRE)--The Silicon Integration Initiative Compact Model Coalition is proud to announce the release of the ASM-ESD diode model, a new electrostatic discharge compact modeling ...
EDN

Matching ESD protection to process geometry

Advanced CMOS process technologies enable IC designers to deliver higher performing devices, but also increase the need for extra board-level ESD protection to ensure the reliability of the end ...
Semiconductor Engineering

ESD Co-Design For High-Speed SerDeS In FinFET Technologies

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device ...
Nature

Electrostatic Discharge Protection in Integrated Circuits

Electrostatic discharge (ESD) protection is an essential facet in the design and operation of modern integrated circuits (ICs). As electronic devices become increasingly miniaturised and complex, ...
Semiconductor Engineering

A New Multi-Stimuli-Based Simulation Method for ESD Design Verification

“This paper analyzes TCAD ESD simulation for both HBM zapping using real-world HBM ESD waveforms as stimuli and TLP testing using square wave TLP pulse trains as stimuli. It concludes that TCAD ESD ...
Electronic Design

It’s Hot, Powering, And Burning CMOS Logic Circuits

Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low. Fig 2. When a CMOS input pin is at logic high or low ...